Generally, in a semiconductor device manufacturing process, a multi-layer fine wiring structure is formed by using a photolithography technique on a semiconductor wafer (hereinafter, referred to as a “wafer”) as a substrate to be processed. The photolithography technique involves the steps of laminating a mask having an opening on an upper layer of an etching target film, e.g., an insulating layer or the like; etching the etching target film via the opening; and patterning a wiring structure by removing the mask.
The mask is formed by coating a photoresist film formed of a photosensitive resin composition on, e.g., a wafer surface, and patterning an opening corresponding to the wring structure in the photoresist film by performing an exposure process and a development process. Therefore, the fineness of the wiring structure is affected by resolution of an exposure device used in the exposure process, and an exposure line width becomes substantially the same as a wiring line width.
FIGS. 13A and 13B show a circuit structure of a NAND type flash memory as an example of a semiconductor device. FIG. 13A is a top view of the circuit structure, and FIG. 13B is a cross sectional view taken along arrow A-A of FIG. 13A. A reference numeral 11 in the drawings indicates a multi-layer structure formed on a surface of a substrate 10, and is referred to as a word line. As shown in FIG. 13B, the word line 11 is formed by laminating e.g., a silicon oxide film 15, a polysilicon film 16, an ONO film 17 and a polysilicon film 18 in that order from the bottom.
Further, a plurality of conductive silicon films 12 are formed on the surface of the substrate 10 so as to cross the word lines 11. The silicon films 12 are arranged to be perpendicular to the word lines 11, thus forming a plurality of parallel lines 12A referred to as active lines which electric current can flow through. Furthermore, crossing parts 19 of the word lines 11 and the silicon films 12, which are surrounded by dotted lines in FIG. 13A, serve as transistors. Charges are accumulated in the ONO films 17 at the crossing parts 19.
When a width L2 of a groove 11A between the word lines 11 is excessively larger than a width L1 of the word line 11, the charges may not be accumulated in the ONO film 17. On the other hand, when L1 is excessively larger than L2, parasitic capacitances between the adjacent polysilicon films (15 and 15, and 17 and 17) in the word lines 11 are increased. Accordingly, the charges may be accumulated between the films, or the electricity may flow between the films (15 and 15, and 17 and 17), which inhibits the function of the device. Therefore, the ratio between L1 and L2 needs to be about 1:1. In order to ensure the function of the device, a width L3 of the line 12A of the silicon film 12 and a gap L4 between the adjacent lines 12A have substantially the same dimensions as those of L1 and L2.
Considering that the dimensions of L1 to L4 need to be substantially the same, a high integration of the crossing parts 19 serving as transistors and the resultant increase in the storage amount can be achieved in the NAND type flash memory more effectively accordingly as L1 to L4 are reduced in size, and the word lines 11 and the active lines 12a are formed more densely. In order to form such a fine wiring as above, it is required to form a pattern of a thin line width densely on an etching target film lying below a photoresist film.
From the above viewpoint, exposure devices capable of performing exposure process for a finer line width has been adopted. In the past, there is used an exposure device for performing an exposure process for a line width of about 130 nm by using a KrF excimer laser. Recently, instead of this, one for performing an exposure process for a line width of about 70 nm by using an ArF excimer laser has been used. In addition, there is being developed a technique for performing an exposure process for a line width of about 40 to 50 nm by using a liquid immersion lithography in which an exposure is carried out via a liquid film formed on a wafer surface by using an ArF excimer. However, in general, an exposure device is high-priced, and the cost increases when changing exposure devices according to a required wiring line width.
Due to growing demands for a further reduction in wiring size, it is required to perform an exposure process for a line width of about 20 to 30 nm. As a higher resolution than can be achieved by the exposure device becomes required, an etching method referred to as a double patterning is being researched. In this double patterning method, an inorganic film of, e.g., SiN or the like is formed as a pattern mask below a photoresist mask by using the photoresist mask. Next, sidewalls are formed at both sides of wall portions of the pattern mask. Thereafter, an underlying layer of the pattern mask is etched using the sidewall as a mask, thus forming a single pattern or double patterns corresponding to a pattern of the pattern mask on the underlying layer. In accordance with this method, it is possible to form on the underlying layer a pattern whose line width is substantially half as large as that of the pattern of the pattern mask with a substantially doubled density.
However, the line width of the photoresist pattern that can be formed by the exposure device is limited. Further, since the ratio between the line width of a mask portion and that of a patterned portion is usually about 1:1 in the photoresist, the ratio between the line width of a mask portion and that of a patterned portion is also about 1:1 in the SiN film serving as the pattern mask below the photoresist film. Therefore, as shown in FIG. 14A, a trimming process is performed to adjust the width of a patterned portion 10B by etching after the patterned portion 10B is formed in a SiN film 10A, so that the ratio between the width of the pattern portion ultimately formed in an etching target film and the gap between adjacent patterned portions becomes about 1:1.
When, however, the trimming is carried out, it is difficult to vertically control the shape of sidewalls of the patterned portion 10B, and therefore a shoulder cut shape is formed at the wall portions forming the patterned portion 10B so that upper parts of the wall portions become thinner as illustrated in FIG. 14B. Thus, sidewalls 10C are formed after the shape of the wall portions as shown in FIG. 14C. Since the sidewalls 10C are formed as such, the underlying layer of the SiN film 10A is etched into an undesired shape. This may lead to a failure in forming the desired pattern in the etching target film.
Further, although the double patterning method is used, it is difficult to form on an etching target film a pattern whose line width is less than about 30 nm in case of exposing the photoresist by an exposure device using an ArF excimer laser. Furthermore, even when the photoresist is exposed by the liquid immersion lithography with the exposure device using an ArF excimer laser, it is practically impossible to form on an etching target film a pattern whose line width is less than about 20 nm. Therefore, as demands for further reduction in wiring size are increased, it is impossible to satisfy the demands by forming a wiring of, e.g., 10 nm.
Japanese Patent Application Publication No. 2006-261307 discloses a method for manufacturing a semiconductor device using the double patterning technique. However, according to this method, the above-described problems cannot be solved, and a CMP process or the like is needed in addition to an etching process, thus increasing the processing time.
Further, there is known a method in which a pattern is formed in a sacrificial film below a photoresist film by being patterned after that of the photoresist film, and then the photoresist film removed, and then a new photoresist film is formed to be so arranged not to be overlapped with the previously formed pattern, and then a pattern is formed in the sacrificial film according to the new pattern, and finally a dense pattern is formed in an etching target film below the sacrificial film. However, the above method also has a drawback in that it is difficult to align the substrate for forming the pattern as above.